1. Field of the Invention
The present invention generally relates to a memory device including a parallel test circuit, and more specifically, to a memory device including a parallel test circuit which overcomes a channel deficiency phenomenon of test equipment by reducing the number of input/output pads.
2. Description of the Prior Art
In general, data should exactly be read or written in a semiconductor memory device such as a dynamic RAM. For the exact read/write operation, even one defective cell should not exist on a chip. However, as the number of cells integrated in one chip increases more and more due to high integration of the semiconductor memory device, the number of defective cells may also increase in spite of improvement of the manufacture process. If the exact test is not performed on these defective cells, the reliability of the semiconductor memory device cannot be secured.
Although it is important to perform a reliable test on devices, a high speed test can also be performed on a great number of cells. Specifically, since reduction of improvement period and test time of a semiconductor memory device directly affects cost of products, the reduction of test time has been the main issue manufacture companies.
When one cell is tested to distinguish pass or fail of cells in a memory chip of a semiconductor memory device, the test of the highly integrated memory device takes much time and causes increase of cost.
As a result, a parallel test mode is used to reduce the test time.
When the same data are read after the same data are written in a plurality of cells, the parallel test determined pass or fail of the cells with an exclusive OR logic circuit. The value of the logic operation is “1” to determine pass of the cells if the same data are read, and the value of the logic operation is “0” to determine fail of the cells if the different data are read, thereby reducing the test time.
FIG. 1 is a diagram illustrating a parallel test structure of a conventional memory device. Here, a parallel test of a 4×32 DRAM is exemplified.
Referring to FIG. 1, since the fail cells are repaired in a half bank unit HALF0-A, HALF0-B, HALF1-A, HALF1-B, HALF2-A, HALF2-B, HALF3-A, and HALF3-B, a parallel test block 1 compresses data of half banks HALF0-A, HALF0-B, HALF1-A, HALF1-B, HALF2-A, HALF2-B, HALF3-A, and HALF3-B at a parallel test mode, and outputs the compressed data to input/output pads DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, and DQ7. Here, the parallel test measures a lot of dies in one test equipment.
As a result, the large number of dies can be measured when four input/output pads DQ are used to reduce the number of channels in the test equipment than when 8 input/output pads DQ are used in the test equipment. However, since data compressed in one bank unit are outputted through four input/output pads DQ, the repair operation is required to be performed simultaneously in one bank unit, thereby reducing the efficiency of the repair operation.